Konyk Hardware Description Language

High-level design with Verilog output.

Konyk HDL is a high-level language for defining complex hardware systems. It operates above Verilog and VHDL to improve productivity, prevent common errors, and still gives precise control over the final design.

Explore the beta See editor support

Overview

Konyk HDL lets you describe hardware at a higher level of abstraction than Verilog or VHDL. It enables faster iteration, fewer mistakes, and clearer intent while still compiling down to synthesizable Verilog.

Higher abstraction

Focus on architecture and behavior instead of low-level wiring.

Productivity gains

Build complex systems faster with fewer boilerplate constructs.

No lock-in

Generate Verilog that can be synthesized by standard toolchains.

Why teams choose Konyk HDL

  • Structured modeling that prevents common RTL errors.
  • Fine-grained control beyond high-level C++ synthesis flows: explicit clock and reset domains, explicit asynchronous signals.
  • Clearer designs that translate directly to synthesizable Verilog.
  • Built for large systems with reusable components.
  • Inherently robust: Enforces strict syntactic and semantic controls to eliminate bugs common in Verilog and VHDL.

Beta status

Konyk HDL is currently in beta. A complete RISC-V system has been fully specified using the language, and tooling is actively expanding.

What is available today

  • An initial set of standard patterns: FSMs, Queues, Sequencers.
  • A fill RISC-V processor (RV32I) specified in Konyk HDL.
  • Compiler pipeline that produces synthesizable Verilog.
  • Early editor support for VS Code and Eclipse.

Tooling and editor support

Boost productivity with syntax awareness, navigation, and editing help while the ecosystem continues to mature.

VS Code

Initial language support with syntax and navigation basics.

Eclipse

Early integration for teams using Eclipse-based workflows.

Command line tooling

Generate Verilog outputs suitable for standard synthesis flows.